1. Field of the Invention
This invention relates generally to an improvement in asynchronous communication, and more specifically to preventing packet underflow and overflow without undue circuit complexity.
2. Description of the Prior Art
In a system with multiple integrated circuit (IC) chips operating at different core frequencies, if the transmitting chip clock frequency is different from the receiving chip clock frequency, there may be packet overflow or underflow problems. A packet overflow problem occurs when the transmitting chip clock frequency is higher than the receiving chip clock frequency, and some packets are dropped at the receiving chip. A packet underflow problem occurs when the transmitting chip clock frequency is lower than the receiving chip clock frequency, and the receiving chip has some clock cycles when there are no valid data packets from the transmitting chip. These packet underflow episodes are sometimes referred to as bubbles.
One prior art solution involves performing the packet processing (namely error correction code decoding, type decoding, initialization, and other basic functions) on the receiving chip side using the clock of the transmitting chip. This requires a significant amount of circuitry in the receiving chip that is controlled by the transmitting chip""s clock. One drawback of this prior art approach is that the control circuitry gets split between the two clock domains, making the design complex, since the two clock domains have to work together in tandem. It also means that some control and status registers, including error-logging registers, need to be present in the transmitting chip clock domain.
FIG. 1 illustrates a prior art approach for transmission and reception of packets between a transmitting chip 130 and a receiving chip 132. Transmitting chip core logic 118 sends data signals to outbound processing circuit 114, and sends and receives clock and control signals from error logs and other control registers 116. In the transmitting chip clock domain 140, inbound processing circuit 102 receives transmitting chip clock 120 and data 122 from outbound processing circuit 114, and provides packets to a synchronizing First-In-First-Out (FIFO) buffer 104, which is read using a receiving chip clock (not shown) and written using the transmitting chip clock 120. Storage FIFO 106 is entirely in the receiving chip clock domain 150 and receives packets from synchronizing FIFO 104. Error logs and other control registers 108 send and receive signals from inbound processing circuit 102, and send and receive signals from synchronizing circuitry 110. Synchronizing circuitry 110 is used to access these error logs and other control registers 108 from the receiving chip clock domain 150. Receiving chip core logic 112 sends and receives signals from synchronizing circuitry 110, and receives data from storage FIFO 106.
This prior art approach handles the packet underflow problem by ensuring that an adequate number of packets in the transaction are gathered by the storage FIFO 106 before sending the transaction to the receiving chip core logic 112. A packet overflow problem is handled by ensuring that the transmitting chip 130 sends a number of idle packets at fixed intervals of time, so that the receiving chip 132 can catch up without requiring the idle packets to go through its synchronizing FIFO buffer 104 into the receiving chip clock domain 150.
For example, a prior art approach for handling the packet overflow problem would set up the transmitting chip 130 to send three or more idle packets every 1000 clock cycles, regardless of whether or not these 1000 clock cycle intervals occur in the middle of a transaction. Furthermore, the prior art approach for handling the packet underflow problem would require a hardware and software mechanism to stop pulling out packet entries from the storage FIFO buffer until a certain number of packet entries are available. Therefore, prior art solutions for overflow and underflow packet problems require separate hardware and software for overflow and underflow, with hardware in the packet path both before and after the synchronizing FIFO buffer, and require substantially continuous processing of the packets with this hardware and software, even in the middle of transactions.
There are several drawbacks to this prior art approach. There is a lot of extra circuitry required to synchronize the registers in the transmitting chip clock domain 140 to the receiving chip clock domain 150. This extra circuitry introduces greater complexity into the design. This approach also makes parts of the circuitry, such as the status and control registers in the transmitting chip clock domain 140 inaccessible, when the transmitting chip 130 is not present, has not been powered on, or is in some kind of reset state. The system software has to operate successfully despite these possibilities; this can require very complex software that is difficult to write and difficult to debug. This is also not a good solution from a high reliability/availability perspective, since the transmitting chip 130 not only affects the link to which the receiving chip 132 is connected, it also affects parts of the receiving chip 132, rendering these parts inaccessible.
One way to get around the latency problem is to design a core in the receiving chip 132 that can deal with bubbles caused by packet underflow. However, this will significantly complicate the design. In addition, increasing design complexity of a system (and the number of components that can fail) generally reduces the overall reliability of the system.
What is needed is a simple implementation that solves both the packet overflow problem and the packet underflow problem using the same mechanism, and which reduces the complexity of the solution by elimination of the control split between the receiving chip and transmitting chip clock domains.
One object of the invention is to provide a simple implementation that solves both the overflow problem and the underflow problem using the same mechanism, and which reduces the solution complexity by elimination of the control split between the receiving chip and transmitting chip clock domains.
A first aspect of the invention is directed to a method for preventing packet underflow and packet overflow for packets sent across an asynchronous link between a transmitter and a receiver, wherein the receiver includes a buffer that can store a number of packets greater than an ideal number of packets. The method includes sending a predetermined number of drop-me warning packets from the transmitter to the receiver across the asynchronous link, sending one or more drop-me packets from the transmitter to the receiver across the asynchronous link, receiving the predetermined number of drop-me warning packets and the one or more drop-me packets in the buffer, compensating for packet overflow when the number of packets in the buffer is greater than the ideal number of packets by skipping at least one drop-me packet in the buffer, so that the ideal number of packets is substantially maintained in the buffer, and compensating for packet underflow when the number of packets is less than the ideal number of packets by stalling access to the buffer for one or more clock cycles, so that the ideal number of packets is substantially maintained in the buffer.
A second aspect of the invention is directed to an asynchronous link for packets sent between a transmitter having a first clock and a receiver having a second clock. The asynchronous link includes a buffer to receive the first clock from the transmitter and receive from the transmitter a number of packets equal to or different from a predetermined ideal number of packets, a read pointer containing a read address for the buffer and a read pointer control circuit to change the read address, wherein the buffer can receive drop-me packets and the read address in the read pointer can skip a drop-me packet in the buffer, and a write pointer containing a write address for the buffer.
These and other objects and advantages of the invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.